Advanced extensible interface (AXI) interconnect network of an advanced microcontroller bus architecture (AMBA) is a conventional bus matrix configuration. Typically, the AXI interconnect network is formed as a bus matrix with a plurality of channels. The plurality of channels is connected to a plurality of masters and slaves by multiplexers and demultiplexers along with an arbitration logic, a buffering logic, a data width conversion logic, a frequency conversion logic and so on. The masters can access different slaves at the same time by way of the AXI interconnect network.
Generally, the AXI interconnect network consists of 5 independent channels: address write (AW), address read (AR), write data (W), read data (R), and write response (B), which provide a powerful support for out-of-order transaction completion. A typical write transaction uses AW, W, and B channels and a typical read transaction uses AR and R channels. These independent channels are connected via associated transaction identifications (IDs) when a transaction is in progress.
In a multilayer multilevel interconnect architecture, multiple master interfaces can be connected to a shared slave interface. Typically, the bus matrix is used to route the transactions from the multiple master interfaces onto the shared slave interface. A slave transaction ID width is generated based on the largest master ID width and number of masters connected to the associated bus matrix using the following equation:slave transaction ID width=largest master ID width+log2(total number of masters)When the total number of masters is not a multiple of 2, log2(total number of master) is rounded to a next integer value.
In the above scenario, all shared slaves' use the same transaction ID widths irrespective of a system level sparse connection, i.e., all the masters may not be connected to all the slaves. In a system with multiple bus matrices, slave transaction ID widths are generated without considering the system level sparse connection, which can lead to requiring more than needed overall increased slave transaction ID width, which in-turn may lead to requiring additional hardware. Further, with increased slave transaction ID widths, it can be difficult to interface with existing standard slave components, such as Cortex™-R4 slave interface.